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19-0545; Rev 0; 6/06
KIT ATION EVALU E AILABL AV
12V PWM Controller with Hot-Swap
General Description Features
o o o o o o o o o o o o o o o 8V to 16V or 5V 10% Input-Voltage Range Integrated Hot-Swap Controller Lossless Valley-Mode Current Sensing Output Voltage Adjustable from 0.8V to 5.5V Voltage-Mode Control External Compensation for Maximum Flexibility Digital Soft-Start Sequencing or Ratiometric Tracking Startup Synchronization Programmable PGOOD Output Programmable Switching Frequency from 100kHz to 1MHz External Frequency Synchronization SYNCIN and SYNCOUT Enable 180 Out-of-Phase Operation Thermal Shutdown and Short-Circuit Protection Space-Saving 5mm x 5mm, 32-Pin TQFN Package
MAX5950
The MAX5950 is a 12V pulse-width modulated (PWM), step-down, DC-DC controller with integrated hot-swap controller. The device operates over the 8V to 16V inputvoltage range or 5V 10% and provides an adjustable output from 0.8V to 5.5V. The device delivers up to 10A of load current with excellent load-and-line regulation. The MAX5950 is optimized for PCIe(R) ExpressModuleTM power-management application. The MAX5950 features a hot-swap controller that provides inrush current control during module insertion and removal, as well as short-circuit protection during normal operation. The MAX5950 features an internal charge pump that provides the gate drive for an external n-channel MOSFET. A DCENO logic output indicates the completion of the inrush cycle. The MAX5950 PWM section utilizes a voltage-mode control scheme for good noise immunity and offers external compensation, allowing for maximum flexibility with a wide selection of inductor values and capacitor types. The device operates at a fixed switching frequency that is programmable from 100kHz to 1MHz and can be synchronized to an external clock signal through the SYNCIN input. The device includes undervoltage lockout (UVLO) and digital soft-start. Protection features include lossless valley-mode current limit, hiccup-mode output short-circuit protection, and thermal shutdown. The MAX5950 is available in a space-saving 5mm x 5mm, 32-pin thin QFN package and is specified for operation over the -40C to +85C extended temperature range. Refer to the MAX5951 data sheet for a pincompatible, general-purpose PWM controller.
Ordering Information
PART MAX5950ETJ+ TEMP RANGE -40C to +85C PINPACKAGE 32 TQFN-EP* PKG CODE T3255-4
+Denotes lead-free package. *EP = Exposed pad.
Applications
SENSE ILIM CS+ FB
Pin Configuration
TOP VIEW
STARTUP 18 PGOOD COMP RT 17 16 15 14 13 SYNCIN SYNCOUT AGND THRESH DCENI DCENO PGI MPWRGD 12 11 10 9 1 PWM_IN 2 PUVLO 3 HSENSE 4 GATE 5 IN 6 HUVLO 7 PWREN 8 PWRFLT
PCIe ExpressModule General 12V-Input PWM Controllers with Hot-Swap Blade Servers RAID Base Stations Work Stations
24 CS- 25 PGND 26 DL 27 DREG 28 LX 29 DH 30 BST 31 REG 32
23
22
21
20
19
MAX5950
+
PCIe is a registered trademark and ExpressModule is a trademark of PCI-SIG Corp.
TQFN (5mm x 5mm)
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
12V PWM Controller with Hot-Swap MAX5950
ABSOLUTE MAXIMUM RATINGS
IN to AGND.............................................................-0.3V to +24V HSENSE, PWM_IN to AGND........................-0.3V to (VIN + 0.3V) GATE to AGND.......................................................-0.3V to +30V GATE to PWM_IN ....................................................-0.3V to +6V PWREN, PWRFLT, MPWRGD, HUVLO, PGI, DCENO to AGND ................................................................-0.3V to +6V BST to AGND..........................................................-0.3V to +30V BST to LX..................................................................-0.3V to +6V CS- to AGND.......................................-0.3V to (VPWM_IN + 0.3V) REG, DREG, PUVLO, DCENI, SYNCIN, THRESH, SENSE to AGND....................................................-0.3V to +6V RT, ILIM, STARTUP, PGOOD, FB, CS+ to AGND ....-0.3V to +6V SYNCOUT, COMP to AGND.....................-0.3V to (VREG + 0.3V) DL to PGND...............................................-0.3V to (VDREG + 6V) DH to LX ....................................................-0.3V to (VBST + 0.3V) PGND to AGND .....................................................-0.3V to +0.3V Input Current (any pin) .....................................................50mA Continuous Power Dissipation 32-Pin TQFN (derate 34.5 mW/C above +70C) ...2758.6mW 32-Pin TQFN (JA) ......................................................+29C/W 32-Pin TQFN (JC)........................................................2.1C/W Operating Ambient Temperature Range .............-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) ............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VPWM_IN = 12V or VIN = VPWM_IN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 100k, RILIM = 60k, CREG = 2.2F, TA = TJ = -40C to +85C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER Input-Voltage Range Standby Supply Current Quiescent Supply Current Switching Supply Current HOT-SWAP UVLO Default Hot-Swap Undervoltage Lockout Threshold Hot-Swap UVLO Hysteresis HUVLO Threshold HUVLO Hysteresis HUVLO Input Impedance HOT-SWAP PWREN CONTROL PWREN Input High-Level Voltage PWREN Input Low-Level Voltage PWREN Input Hysteresis PWREN Input Pullup Resistance PWREN Clamp Voltage PWREN High-to-Low Deglitch Time HOT-SWAP CIRCUIT-BREAKER COMPARATOR Circuit-Breaker Threshold HSENSE Input Bias Current HOT-SWAP GATE CONTROL GATE Charge Current GATE High Voltage IGATE VGATE - VPWM_IN, sourcing 1A 4 4.7 5 5.4 6 6.1 A V VCB VIN - VHSENSE VHSENSE = 12V 553 -1 613 673 +1 mV A IPWREN = 1mA 6.5 50 260 100 4.8 10.5 15.0 160 2 0.8 V V mV k V ms 180 VHUVLO VHUVLO rising 1.202 VIN rising 6.7 0.7 1.220 122 310 500 1.238 7.3 V V V mV k SYMBOL VIN CONDITIONS VIN = VPWM_IN = VREG = VDREG (Note 2) VIN = 16V, VPWM_IN = VHUVLO = 0V VIN = VPWM_IN = 16V, VFB = 0.9V VIN = VPWM_IN = 16V, VFB = 0V MIN 8 4.5 1.0 2.3 6 TYP MAX 16 5.5 1.6 3.7 9 V mA mA mA UNITS
2
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12V PWM Controller with Hot-Swap
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VPWM_IN = 12V or VIN = VPWM_IN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 100k, RILIM = 60k, CREG = 2.2F, TA = TJ = -40C to +85C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER GATE Pulldown Resistance Hot-Swap FET Enhancement Threshold Hot-Swap FET Enhancement Hysteresis HOT-SWAP LOGIC OUTPUTS DCENO Internal Pullup Current PWRFLT, MPWRGD Input Leakage PWRFLT, MPWRGD, DCENO Output Voltage Low MPWRGD Power-On-Reset Time HOT-SWAP LOGIC INPUTS PGI Input High-Level Voltage PGI Input Low-Level Voltage PGI Input Hysteresis PGI Blanking Time from DCENO High PWM UVLO Default PWM Undervoltage Lockout Threshold PWM Undervoltage Lockout Hysteresis PUVLO Threshold PUVLO Hysteresis PUVLO Input Impedance PWM DCENI CONTROL DCENI Comparator Input Common-Mode Range DCENI Comparator Offset DCENI Comparator Hysteresis DCENI Input Current THRESH Operating Voltage Range THRESH Input Current Default DCENI Threshold PWM PGOOD OUTPUT SENSE Threshold SENSE Hysteresis VSENSE rising 788 800 100 812 mV mV VTHRESH > 0.6V VTHRESH < 0.3V VTHRESH < 0.3V -1 0.6 -1.5 -5 1.202 1.22 VDCENI - VTHRESH 0 -10 100 +1 2.5 +1.0 +1 1.238 3 +10 V mV mV A V A V 180 VPUVLO VPUVLO rising 1.202 VPWM_IN rising 6.7 0.7 1.22 122 310 500 1.238 7.3 V V V mV k 100 260 165 250 2 0.8 V V mV ms Sinking 2.4mA 100 165 -1 10 +1 50 250 A A mV ms SYMBOL CONDITIONS Sinking 1mA to AGND VGATE rising 3.45 4.0 70 MIN TYP MAX 40 4.65 UNITS V mV
MAX5950
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3
12V PWM Controller with Hot-Swap MAX5950
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VPWM_IN = 12V or VIN = VPWM_IN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 100k, RILIM = 60k, CREG = 2.2F, TA = TJ = -40C to +85C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER SENSE Input Bias Current PGOOD Internal Pullup Current PGOOD Output-Voltage Low INTERNAL VOLTAGE REGULATOR Output-Voltage Set Point Line Regulation Load Regulation PWM OSCILLATOR Oscillator Frequency Range fSW VSYNCIN = 0V, fSW = 5 x 1010 / RRT Hz TA = TJ = +25C Oscillator Accuracy TA = TJ = -40C to +85C RT Voltage Maximum Duty Cycle SYNCIN High Level Voltage SYNCIN Low Level Voltage SYNCIN Pulldown Resistor SYNCIN Rising to SYNCOUT Falling Delay SYNCIN Falling to SYNCOUT Rising Delay Maximum SYNCIN Frequency SYNCOUT Voltage High SYNCOUT Voltage Low PWM ERROR AMPLIFIER FB Input Range FB Input Current COMP Output-Voltage Range Open-Loop Gain Unity-Gain Bandwidth Reference Voltage PWM COMPARATOR Comparator Offset Voltage Comparator Propagation Delay PWM DIGITAL SOFT-START Soft-Start Duration Reference Voltage Steps 1024 128 6.3 Clocks Steps mV 0.3 40 V ns fGBW VREF ICOMP = -500A to +500A 792 ICOMP = -500A to +500A 0 -250 0.25 80 2.5 800 808 VREF +250 VREG - 0.5 V nA V dB MHz mV VHSYNCOUT ISYNCOUT = +1.2mA VLSYNCOUT ISYNCOUT = -2.4mA 1 VREG - 0.1 50 50 100 10 30 VRT 50k RRT 500k VSYNCIN = 0V, VPWM_IN = 12V 82 2.1 0.8 150 fSW 500kHz fSW > 500kHz fSW 500kHz fSW > 500kHz 100 -2.5 -4 -3.5 -5 2 88 1000 +2.5 +4 +3.5 +5 V % V V k ns ns MHz V mV % kHz VREG VPWM_IN = 8V to 16V IREG = 0 to 50mA 4.7 5.3 1 150 V mV/V mV IPGOOD = -2.4mA SYMBOL CONDITIONS MIN -1 10 50 TYP MAX +1 UNITS A A mV
4
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12V PWM Controller with Hot-Swap
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VPWM_IN = 12V or VIN = VPWM_IN = VREG = 5V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 100k, RILIM = 60k, CREG = 2.2F, TA = TJ = -40C to +85C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER PWM RAMP GENERATOR Ramp Amplitude PWM CURRENT-LIMIT COMPARATOR AND HICCUP MODE Cycle-by-Cycle Valley CurrentLimit Threshold Adjustment Range Cycle-by-Cycle Valley CurrentLimit Threshold Tolerance ILIM Reference Current ILIM Reference Current Tempco CS+, CS- Input Bias Current PWM HICCUP MODE Number of Cumulative CurrentLimit Events to Hiccup Number of Consecutive NonCurrent Limit Cycles to Clear NCL Hiccup Timeout PWM STARTUP INPUT STARTUP Threshold STARTUP Threshold Hysteresis Internal Pullup Current STARTUP Output Voltage Low PWM DH DRIVER Peak Source Current Peak Sink Current DH Resistance Sourcing DH Resistance Sinking PWM DL DRIVER Peak Source Current Peak Sink Current DL Resistance Sourcing DL Resistance Sinking Break-Before-Make Time THERMAL SHUTDOWN Thermal-Shutdown Temperature Thermal-Shutdown Hysteresis TJ rising +135 15 C C VDL = 0V, pulse width < 100ns, VDREG = 5V VDL = 5V, pulse width < 100ns, VDREG = 5V IDL = 50mA, VDREG = 5V IDL = -50mA, VDREG = 5V 2 2 1 1 25 3 3 A A ns VDH,LX = 0V, pulse width < 100ns, VBST, LX = 5V VDH,LX = 5V, pulse width < 100ns, VBST, LX = 5V IDH = 50mA, VBST, LX = 5V IDH = -50mA, VBST, LX = 5V 2 2 1 1 3 3 A A ISTART ISTARTUP = -2.4mA VSUT VSUT rising 1.1 250 10 50 1.9 V mV A mV NCL NCLR NHT 8 3 512 Clocks Clocks Clocks VCS+ = 0V, VCS- = -0.3V, current out of the CS_ -1 Limit = VILIM / 10 VILIM = 0.5V VILIM = 3.5V VILIM = 0 to 3.5V, TA = TJ = +25C 50 44.5 330 19 20 3333 +20 350 55.5 366 21 mV mV A ppm/C A 1.8 V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5950
Note 1: Limits at -40C are guaranteed by design and are not production tested. Note 2: For 5V applications, connect REG directly to PWM_IN.
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5
12V PWM Controller with Hot-Swap MAX5950
Typical Operating Characteristics
(Typical Application Circuits. VIN = VPWM_IN = 12V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 49.9k, RILIM = 48.7k, CREG = 2.2F, TA = +25C, unless otherwise noted.)
HOT-SWAP UNDERVOLTAGE LOCKOUT THRESHOLD vs. TEMPERATURE
MAX5950 toc01
CIRCUIT-BREAKER THRESHOLD vs. TEMPERATURE
MAX5950 toc02
PWREN DELAY vs. TEMPERATURE
MAX5950 toc03
1.30
660
13
1.27
640 VIN - VHSENSE (mV)
12 PWREN DELAY (ms)
VHUVLO (V)
1.24
620
11
1.21
600
10
1.18
580
9
1.15 -40
-15
10
35
60
85
560 -40
-15
10
35
60
85
8 -40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
MPWRGD POWER-ON RESET TIME vs. TEMPERATURE
MAX5950 toc04
GATE CHARGE CURRENT vs. TEMPERATURE
MAX5950 toc05
GATE HIGH VOLTAGE vs. TEMPERATURE
MAX5950 toc06
200 MPWRGD POWER-ON RESET TIME (ms) 190 180 170 160 150 140 -40 -15 10 35 60
6.00 5.75 5.50 IGCC (A) 5.25 5.00 4.75 4.50 4.25 4.00 VIN = 8V - 16V
6.0
5.8 VGATE - VPWM_IN (V)
5.6
5.4
5.2
85
-40
-15
10
35
60
85
5.0 -40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
PWM UNDERVOLTAGE LOCKOUT THRESHOLD vs. TEMPERATURE
MAX5950 toc07
DEFAULT DCENI THRESHOLD vs. TEMPERATURE
MAX5950 toc08
SENSE THRESHOLD vs. TEMPERATURE
MAX5950 toc09
1.30
1.30
808
VPUVLO (V)
1.24
1.24
SENSE THRESHOLD (mV) 85
1.27
1.27 DCENI THRESHOLD (V)
804
800
1.21
1.21
796
1.18
1.18
792
1.15 -40
-15
10
35
60
85
1.15 -40
-15
10
35
60
788 -40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
6
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12V PWM Controller with Hot-Swap MAX5950
Typical Operating Characteristics (continued)
(Typical Application Circuits. VIN = VPWM_IN = 12V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 49.9k, RILIM = 48.7k, CREG = 2.2F, TA = +25C, unless otherwise noted.)
REG OUTPUT VOLTAGE vs. TEMPERATURE
MAX5950 toc10
REG OUTPUT VOLTAGE vs. LOAD CURRENT
MAX5950 toc11
REG OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX5950 toc12
5.15 5.10 5.05 VREG (V)
5.15 5.10 5.05 VREG (V) 5.00 4.95 4.90 4.85
5.06
5.04
5.00 4.95 4.90 4.85 -40 -15 10 35 60 85 TEMPERATURE (C)
VREG (V) 0 50
5.02
5.00
4.98
4.96 10 20 30 40 8 10 12 PWM_IN (V) 14 16 IREG (mA)
SWITCHING FREQUENCY vs. RRT
MAX5950 toc13a
SWITCHING PERIOD vs. RRT
MAX5950 toc13b
SWITCHING FREQUENCY vs. TEMPERATURE
RRT = 49.9k 1020 1010 fSW (kHz) 1000 990 980
MAX5950 toc14
1000 900 800 700 fSW (kHz) 600 500 400 300 200 100
10 9 SWITCHING PERIOD (s) 8 7 6 5 4 3 2 1
1030
970 50 100 150 200 250 300 350 400 450 500 RRT (k) -40 -15 10 35 60 85 TEMPERATURE (C)
50 100 150 200 250 300 350 400 450 500 RRT (k)
FB REFERENCE VOLTAGE vs. TEMPERATURE
MAX5950 toc15
OPEN-LOOP GAIN/PHASE vs. FREQUENCY
180 160 PHASE (deg) 140 120 100 80 60 0 10 100 1k 10k 100k 1M 40 10M VALLEY CURRENT-LIMIT THRESHOLD (mV) 100 90 80 70 GAIN (dB) 60 50 40 30 20 10 0 -10 -20
MAX5950 toc16
VALLEY CURRENT-LIMIT THRESHOLD vs. VILIM
MAX5950 toc17
808
200
350 300 250 200 150 100 50 500 1000 1500 2000 VILIM (mV) 2500 3000
804
VREF (mV)
800
796
792
788 -40
-15
10
35
60
85
3500
TEMPERATURE (C)
FREQUENCY (Hz)
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7
12V PWM Controller with Hot-Swap MAX5950
Typical Operating Characteristics (continued)
(Typical Application Circuits. VIN = VPWM_IN = 12V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 49.9k, RILIM = 48.7k, CREG = 2.2F, TA = +25C, unless otherwise noted.)
VALLEY CURRENT-LIMIT THRESHOLD vs. TEMPERATURE
MAX5950 toc18
DL, DH DRIVER ON-RESISTANCE vs. TEMPERATURE
MAX5950 toc19
QUIESCENT SUPPLY CURRENT vs. TEMPERATURE
MAX5950 toc20
140 VALLEY CURRENT-LIMIT THRESHOLD (mV) RILIM = 48.7k 130 120 110 100 90 80 70 60 -40 -15 10 35 60
2.00 VFB = 0.9V 1.75 DRIVER ON-RESISTANCE () 1.50 1.25 1.00 0.75 0.50 RESISTANCE SINKING RESISTANCE SOURCING
3.25
3.00 VPWM_IN = 16V IQ (mA) 2.75 VPWM_IN = 12V
2.50
2.25 0.25 0 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C) 2.00 -40
-15
10
35
60
85
TEMPERATURE (C)
SWITCHING SUPPLY CURRENT vs. TEMPERATURE
MAX5950 toc21
STARTUP WAVEFORM
MAX5950 toc22a
STARTUP WAVEFORM
MAX5950 toc22b
6.75
VIN = 12V IN 10V/div PWREN 5V/div GATE 1OV/div PWM_IN 1OV/div VGATE 1OV/div VPWM_IN 1OV/div IINRUSH 1A/div
6.50 VPWM_IN = 16V ISW (mA) 6.25 VPWM_IN = 12V
6.00
5.75
5.50 -40
-15
10
35
60
85
4ms/div
1ms/div PWREN SWITCHING FROM HIGH TO LOW
TEMPERATURE (C)
PGOOD SEQUENCING (FIGURE 1)
MAX5950 toc23a
STARTUP
MAX5950 toc23b
DCEN0 = DCENI1 5V/div OUT1 1V/div OUT2 1V/div OUT3 1V/div
VPWM_IN = 12V DCENO = DECENI1 5V/div PGI 5V/div
MPWRGD 2V/div PGOOD3 = PG1 5V/div 1ms/div PWREN SWITCHING FROM HIGH TO LOW 40ms/div PWREN SWITCHING FROM HIGH TO LOW PWRFLT 2V/div
8
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12V PWM Controller with Hot-Swap
Typical Operating Characteristics (continued)
(Typical Application Circuits. VIN = VPWM_IN = 12V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 49.9k, RILIM = 48.7k, CREG = 2.2F, TA = +25C, unless otherwise noted.)
STARTUP SEQUENCING (FIGURE 1)
MAX5950 toc23c
MAX5950
TRACKING (FIGURE 1)
MAX5950 toc23d
DCEN0 = DCENI1 = STARTUP 5V/div OUT1 1V/div OUT2 1V/div OUT3 1V/div
DCEN0 - DCENI_ = STARTUP_ 5V/div OUT1 1V/div OUT2 1V/div OUT3 1V/div
PGI = PGOOD3 5V/div CSTART = 1F 2ms/div PWREN SWITCHING FROM HIGH TO LOW 400s/div PWREN SWITCHING FROM HIGH TO LOW
PGOOD_ 5V/div
STARTUP FAULT
MAX5950 toc24a
STARTUP FAULT
MAX5950 toc24b
OVERLOAD RESPONSE
MAX5950 toc25a
0V
DCEN0 = DCENI1 = STARTUP_ 5V/div OUT1 1V/div
0V
0V
0V 0V
DCEN0 = DCENI1 = STARTUP_ 5V/div VOUT1 1V/div PGI = PGOOD3 1V/div MPWRGD 2V/div MPWRFLT 2V/div
0V 0V
OUT1 1V/div IOUT1 2A/div LX 10V/div DL 10V/div STARTUP 5V/div 4s/div
0V 0V
OUT2 2V/div OUT3 SHORTED TO PGND 2V/div PGI = PGOOD3 5V/div 20ms/div PWREN SWITCHING FROM HIGH TO LOW
0V 0V
0V
0V
0V 40ms/div PWREN SWITCHING FROM HIGH TO LOW OUT3 SHORTED TO PGND
0V
OVERLOAD RESPONSE (HICCUP MODE)
MAX5950 toc25b
SHORT-CIRCUIT RESPONSE
MAX5950 toc26a
SHORT-CIRCUIT RESPONSE (HICCUP MODE)
MAX5950 toc26b
OUT1 1V/div IOUT1 2A/div LX 10V/div DL 10V/div STARTUP 5V/div 400s/div 2s/div
VOUT1 SHORTED TO PGND 1V/div
OUT1 SHORTED TO PGND 1V/div IOUT1 2A/div
LX 10V/div DL 5V/div STARTUP 5V/div 400s/div
LX 10V/div DL 10V/div STARTUP 5V/div
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9
12V PWM Controller with Hot-Swap MAX5950
Typical Operating Characteristics (continued)
(Typical Application Circuits. VIN = VPWM_IN = 12V, VDREG = VREG, VPGND = 0V, VSYNCIN = 0V, RRT = 49.9k, RILIM = 48.7k, CREG = 2.2F, TA = +25C, unless otherwise noted.)
SYNCHRONIZATION
MAX5950 toc27
BREAK-BEFORE-MAKE TIME
MAX5950 toc28a
BREAK-BEFORE-MAKE TIME
MAX5950 toc28b
SYNCIN2 = SYNCOUT1 5V/div LX1 10V/div
LX 5V/div
LX1 5V/div
DL 5V/div
DL1 5V/div IOUT1 = 0.5A
DL1 5V/div
200ns/div
10ns/div
10ns/div
EFFICIENCY vs. LOAD CURRENT
MAX5950 toc29
EFFICIENCY vs. LOAD CURRENT
MAX5950 toc30
EFFICIENCY vs. LOAD CURRENT
90 80 EFFICIENCY (%) 70 60 50 40 30 20 VIN = 12V VIN = 16V VIN = 5V VIN = 8V
MAX5950 toc31
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 VOUT = 3.3V VPWM_IN = 8V VPWM_IN = 12V VPWM_IN = 5V VPWM_IN = 16V
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 VOUT = 2.5V 0.8 VPWM_IN = 16V VPWM_IN = 12V VPWM_IN = 8V VPWM_IN = 5V
100
10 0 0 0.5 1.0 1.5
VOUT = 1.2V 2.0 2.5
1.0
1.0
ILOAD (A)
ILOAD (A)
ILOAD (A)
LOAD-TRANSIENT RESPONSE
MAX5950 toc32
LOAD-TRANSIENT RESPONSE
MAX5950 toc33
2.5A IOUT1 1A/div 0A 1.25A 0A IOUT1 1A/div
VOUT1 50mV/div AC-COUPLED
VOUT1 20mV/div AC-COUPLED
400s/div
400s/div
10
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12V PWM Controller with Hot-Swap MAX5950
Pin Description
PIN 1 2 3 4 NAME PWM_IN PUVLO HSENSE GATE PWM Controller Input Voltage PWM UVLO Divider Center Point. Use an external divider to override the internal PWM UVLO divider. The rising threshold is set to 1.220V with 122mV hysteresis. Leave PUVLO unconnected for the default PWM UVLO. Hot-Swap Negative-Sense Input. Connect HSENSE close to the hot-swap FET source. Hot-Swap Gate-Drive Output. Connect GATE to the gate of an external n-channel MOSFET. Supply Input Connection. Connect to an external voltage source from 8V to 16V. For 5V input application, connect IN = PWM_IN = REG to a 5V 10% source. Connect an external divider from IN to PUVLO to AGND to lower the startup voltage. Connect an external divider from IN to HUVLO to AGND to override the hot-swap undervoltage lockout threshold. Center Point of the Hot-Swap UVLO Divider. Use an external divider to override the internal hot-swap UVLO divider. The rising threshold is 1.220V with 120mV hysteresis. Leave HUVLO unconnected for the default hot-swap UVLO. Active-Low Power-Enable Input. Pull PWREN low for at least 10ms for the hot-swap to commence. Active-low PWREN is internally pulled high. Active-Low Power-Fault Output. This open-drain output latches low when a hot-swap or PWM fault occurs. Pulse PWREN high, then low or cycle the power supply to clear the latch. Active-Low Module Power-Good Output. This open-drain output goes low 165ms after the hot-swap is completed. MPWRGD indicates that both hot-swap and downstream DC-DC switchers are operating properly. Power-Good Input. Connect PGI to the PGOOD outputs of the DC-DC switchers. PGI is used to indicate that all the output voltages of the DC-DC switchers are in range. PGI blanks for 165ms after the hot-swap is completed to allow for DC-DC startup. The hot-swap circuit shuts down if PGI is not pulled high before the blanking period ends. DC-DC Enable Output. This output goes high once the hot-swap is completed. Use DCENO to enable downstream DC-DC switchers. DC-DC Enable Input. DCENI must be above VTHRESH for the PWM controller to start. Connect to REG if not used. DC-DC Enable Input Threshold Set. Connect a resistive divider from REG to THRESH to AGND to set the DCENI threshold. Connect to ground for a default threshold of 1.220V. Analog Ground Connection. Solder the exposed pad to a large AGND plane. Connect AGND and PGND together at one point near the input bypass capacitor return terminal. Synchronization Output. SYNCOUT is a synchronization signal to drive the SYNCIN of a second MAX5950/MAX5951, if used. Leave SYNCOUT unconnected when not used. Synchronization Input. SYNCIN accepts the SYNCOUT from another MAX5950/MAX5951 and shifts switching by 180, allowing the reduction of the input bypass capacitors. When used, drive with a frequency at least 20% higher than the frequency programmed through the RT pin. If phase staggering is desired, use 50% duty cycle. Connect SYNCIN to AGND when not used. Oscillator Timing Resistor Connection. Connect a 500k to 50k resistor from RT to AGND to program the switching frequency from 100kHz to 1MHz. Startup Input. STARTUP coordinates simultaneous soft-start for multiple converters. See the Tracking (STARTUP) section. Power-Good Output. PGOOD output goes high when SENSE is above VREF and STARTUP is high. Error Amplifier Output. Connect COMP to the compensation feedback network. FUNCTION
5
IN
6
HUVLO
7 8
PWREN PWRFLT
9
MPWRGD
10
PGI
11 12 13 14 15
DCENO DCENI THRESH AGND SYNCOUT
16
SYNCIN
17 18 19 20
RT STARTUP PGOOD COMP
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12V PWM Controller with Hot-Swap MAX5950
Pin Description (continued)
PIN 21 22 NAME FB SENSE FUNCTION Feedback Regulation Point. Connect to the center tap of a resistive divider from the converter output to AGND to set the output voltage. The FB voltage regulates to the reference voltage. Output Voltage Sense. Connect a resistive divider from the converter output to SENSE to AGND to monitor the programmed output voltage. SENSE is compared to the internal reference, VREF. Valley Current-Limit Set Output. Connect a 25k to 175k resistor, RILIM, from ILIM to AGND to program the valley current-limit threshold from 50mV to 350mV. ILIM sources 20A out to RILIM. The resulting voltage divided by 10 is the valley current limit. Alternatively, a resistive divider from REG to ILIM to AGND can be used to set the valley current limit. Positive Current-Sense Input. Connect CS+ to the synchronous MOSFET source (connected to PGND). Negative Current-Sense Input. Connect CS- to the synchronous MOSFET drain (connected to LX). Power-Ground Connection. Connect the input filter capacitor's negative terminal, the source of the synchronous MOSFET, and the output filter capacitor's return to PGND. Connect externally to AGND at a single point near the input capacitor return terminal. Low-Side Gate-Driver Output. DL is the gate-driver output for the synchronous MOSFET. Gate-Drive Supply for the Low-Side MOSFET Driver. Connect externally to REG and anode of the boost diode. Source Connection of the High-Side MOSFET and Drain Connection of the Synchronous MOSFET. Connect the inductor and the negative side of the boost capacitor to LX. High-Side Gate-Driver Output. DH drives the gate of the high-side MOSFET. High-Side Gate-Driver Supply. Connect BST to the cathode of the boost diode and to the positive terminal of the boost capacitor. 5V Regulator Output. Bypass with a 2.2F ceramic capacitor to AGND. Exposed Pad. Connect the exposed pad to AGND.
23
ILIM
24 25 26 27 28 29 30 31 32 --
CS+ CSPGND DL DREG LX DH BST REG EP
Detailed Description
The MAX5950 is a PWM, step-down, DC-DC controller with integrated hot-swap controller. The device operates over the 8V to 16V or 5V 10% (VIN = VPWM_IN = VREG) input-voltage range and provides an adjustable output from 0.8V to 5.5V. The device delivers up to 10A of load current with excellent load-and-line regulation. The MAX5950 features a hot-swap controller that provides inrush current control during module insertion and removal, as well as short-circuit protection during normal operation. Normally, when a line card is plugged into a live backplane, the card's discharged filter capacitors provide a low impedance that can momentarily cause the main power supply to collapse. The MAX5950 provides inrush current limiting by slowly enhancing the pass transistor (nMOS) when the board is plugged in, allowing the system to stabilize safely. The device provides short-circuit protection by disconnecting the load
12
in the event of a fault condition. The MAX5950 features an internal charge pump that provides the gate drive for the external n-channel MOSFET. The MAX5950 PWM controller utilizes a voltage-mode control scheme for good noise immunity and offers external compensation, allowing for maximum flexibility with a wide selection of inductor values and capacitor types. The device operates at a fixed switching frequency that is programmable from 100kHz to 1MHz and can be synchronized to an external clock signal through the SYNC input. The device includes UVLO and digital soft-start. Protection features include valleymode current limit, hiccup-mode output short-circuit protection, and thermal shutdown. The MAX5950 is optimized for PCIe ExpressModule power-management application. Table 1 shows the PCIe ExpressModule power-supply rail requirements.
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12V PWM Controller with Hot-Swap MAX5950
Table 1. PCIe ExpressModule Power-Supply Rail Requirements
POWER RAIL +12V Bulk Voltage Tolerance Continuous Current Initial Hot-Plug Capacitance Input Capacitance 15% (max) 2.08A (max) 5000pF (max) 500F (max) 15% (max) 4.17A (max) 5000pF (max) 500F (max) SINGLEWIDE DOUBLEWIDE POWER RAIL +3.3VAUX Voltage Tolerance Continuous Current Peak Precharge Current Input Capacitance Precharge Pin Timing 10% (max) 475mA (max) 475mA (peak) 150F (max) 3ms (max) 10% (max) 950mA (max) 950mA (peak) 300F (max) 3ms (max) SINGLEWIDE DOUBLEWIDE
Notes For Table 1: 1. The +12V power hot-swap circuits are located on the module. 2. Currents during hot insertion do not exceed the module maximum continuous current. 3. The module and connector are not damaged during hot removal or insertion. 4. The +3.3VAUX power precharges the module's +3.3VAUX input capacitors during hot insertion through first precharge pin mating. 5. Peak precharge current during hot insertion is determined by the value of the precharge resistor. Single wide example: precharge resistor = +3.3V/475mA = 7m. 6. +3.3VAUX precharge pin timing is the maximum time guaranteed during hot insertion from the +3.3VAUX precharge pin mating to the main power pin's mating. The time constant with the maximum input capacitance and precharge resistor do not exceed 1/3 of the precharge pin timing. 7. Example: 150F x 7 = 1ms (which is 1/3 the maximum precharge pin timing of 3ms). 8. The maximum current slew rate for each add-in module is no more than 0.1A/s. 9. Each add-in module limits its capacitance on each power rail at the backplane connector to that listed in the above table. 10. Continuous current = the highest averaged current value over any 1s period.
Hot-Swap Controller
Startup and Undervoltage Lockout
The startup period begins 10ms after VIN exceeds the default hot-swap UVLO threshold (7V typ) and PWREN is low. This prevents the MAX5950 from turning on the external MOSFET until VIN exceeds the lockout threshold for 10ms to protect the external MOSFET from insufficient gate-drive voltage. The 10ms timeout ensures that the board is fully plugged into the backplane and that IN is stable. Any negative input-voltage transient at IN below the UVLO threshold resets the device and initiates a new startup cycle. Override the internal hot-swap UVLO divider by connecting a resistive divider from IN to HUVLO to AGND. The HUVLO threshold is 1.220V with 120mV hysteresis. During startup, the MAX5950 limits the inrush current by controlling the external n-channel MOSFET gate voltage, thus slowly enhancing the MOSFET.
threshold, 600mV (typ). The MAX5950 quickly forces and latches the MOSFET off when the circuit-breaker threshold is reached.
DCENO, PWRFLT, MPWRGD
The MAX5950 integrates a DC-DC enable-output (DCENO) that goes high after hot-swapping is completed and PGI has been driven high. Use DCENO to enable downstream PWM controllers and allow a smooth transition from inrush to power mode. The device features an open-drain power-good output (MPWRGD) that goes low 165ms after hot-swap is completed and PGI has been driven high. MPWRGD low indicates that both hot-swap and downstream DC-DC converters are operating properly. The device includes an open-drain power-fault output (PWRFLT) that latches low when a fault is detected by the hot-swap controller. Possible faults include a circuit-breaker event, a thermal-shutdown event, or if PGI is not pulled high within 165ms after DCENO goes high. When such a fault is detected, the MAX5950 forces and latches off the inrush-controlled MOSFET, and DCENO goes low to shut down the DC-DC converters. Pulse PWREN high, then low or cycle the power supply to clear the latch.
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Normal Operation (Circuit Breaker)
In normal operation, the device provides short-circuit protection by monitoring the voltage drop across the onresistance of the n-channel MOSFET (VIN - VHSENSE), and comparing the voltage drop to the circuit-breaker
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12V PWM Controller with Hot-Swap MAX5950
PWREN, PGI
The active-low power-enable input, PWREN, is internally pulled high. Pull PWREN low for at least 10ms for the hot-swap to commence. Connect PGI to the PGOOD outputs of the DC-DC converters. PGI is used to indicate that all the output voltages of the DC-DC converters are in range. PGI blanks for 165ms after the hot-swap is completed to allow for the DC-DC converters to startup.
MOSFET Gate Drivers (DH, DL)
The high-side (DH) and low-side (DL) drivers drive the gates of the external n-channel MOSFETs. The drivers' 2A peak source-and-sink current capability provides ample drive to assure fast rise and fall times of the switching MOSFETs. Short rise and fall times minimize switching losses. For low-output voltage applications where the duty cycle is less than 50%, choose a highside MOSFET (Q2) with a moderate RDS(ON). Choose a low-side MOSFET (Q1) with a very low RDS(ON). The gate-driver circuitry also provides a break-beforemake time (25ns typ) to prevent shoot-through currents during transition.
PWM Controller
PWM UVLO
VPWM_IN must exceed the default PWM UVLO threshold (7V typ) before any PWM operation can commence. The UVLO circuitry keeps the MOSFET drivers, oscillator, and all the internal circuitry shut down to reduce current consumption. Override the internal PWM UVLO divider by connecting an external resistive divider from IN to PUVLO to AGND. The PUVLO threshold is 1.220V with 120mV hysteresis.
Oscillator/Synchronization Input (SYNCIN)/ Synchronization Output (SYNCOUT)
Use an external resistor at RT to program the MAX5950 switching frequency from 100kHz to 1MHz. Choose the appropriate resistor at RT to calculate the desired output switching frequency (fSW): fSW (Hz) = (5 x 1010) / RRT () Connect an external clock (SYNCOUT from another MAX5950/MAX5951) at SYNCIN for external clock synchronization. For proper synchronization, the external frequency must be at least 20% higher than the frequency programmed through the RT input. If SYNCIN is 50% duty cycle, SYNCOUT is shifted by 180, allowing the reduction of the DC-DC converter input bypass capacitor. SYNCOUT is a synchronization signal that is used to drive the SYNCIN of a second MAX5950/MAX5951.
Digital Soft-Start
The MAX5950 soft-start feature allows the load voltage to ramp up in a controlled manner, eliminating outputvoltage overshoot. Soft-start begins after V PWM_IN exceeds the UVLO threshold. The soft-start circuitry gradually ramps up the reference voltage. This controls the rate of rise of the output voltage and reduces input surge currents during startup. The soft-start duration is 1024 clock cycles. The output voltage is incremented through 128 equal steps. The output reaches regulation when soft-start is completed, regardless of output capacitance and load.
Tracking (STARTUP)
The STARTUP input in conjunction with digital soft-start provides simple ratiometric tracking. When using multiple MAX5950s/MAX5951s, in addition to connecting SYNCIN and SYNCOUT signals appropriately, connect the STARTUP of all the devices together. STARTUP synchonizes the soft-start of all the devices' references, and hence their respective output voltages track ratiometrically. See Figure 1 and the Typical 0perating Circuits. The STARTUP input has an internal 10A pullup current, but can be driven by external logic. When using multiple converters, connect the STARTUP of all the devices together.
Internal Linear Regulator (REG)
REG is the output terminal of a 5V LDO, which is powered from PWM_IN and provides power to the IC. Bypass REG to GND with a 2.2F ceramic capacitor. Place the capacitor physically close to the MAX5950 to provide good bypassing. REG is intended for powering only the internal circuitry and should not be used to supply power to external loads.
Low-Side MOSFET Driver Supply (DREG)
DREG is the supply input for the low-side MOSFET driver. Connect DREG to REG externally. Adding an RC filter (5 and 2.2F ceramic capacitor) from REG to DREG filters out the high-peak currents of the MOSFET drivers.
High-Side MOSFET Driver Supply (BST)
BST supplies the power for the high-side MOSFET drivers. Connect the bootstrap diode from BST to DREG (anode at DREG and cathode at BST). Connect a bootstrap 1F ceramic capacitor between BST and LX.
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12V PWM Controller with Hot-Swap MAX5950
STARTUP SEQUENCING PGI DCENI1 REG1 DCENI1 DCENI1 THRESH1 THRESH1 THRESH1 PGOOD1 PGOOD1 PGOOD1 DCENI2 DCENI2 REG2 THRESH2 PGOOD2 THRESH2 DCENI2 THRESH2 PGI DCEN0 PGOOD SEQUENCING
TRACKING PGI DCENO
PGOOD2 PGOOD2 DCENI3 DCENI3 REG3 THRESH3 DCENI3 PGOOD3 THRESH3 STARTUP1 THRESH3
STARTUP2 PGOOD3 STARTUP3 STARTUP1 DCENO
PGOOD3 STARTUP1
STARTUP2 STARTUP2 STARTUP3 STARTUP3 CSTART
Figure 1. Tracking, STARTUP Sequencing, and PGOOD Sequencing Configurations
Startup Sequencing (DCENI, THRESH)
The DCENI input must be above VTHRESH for the PWM controller to start. By connecting the DCENI inputs of multiple devices together and having different start thresholds (VTHRESH_), the startup of the PWM controllers can be staggered to provide power sequencing.
Connect a resistive divider from REG to THRESH to AGND to set the start thresholds of each device between 0.6V and 2.5V. Connect THRESH to AGND to produce a default 1.220V threshold for DCENI. Connecting THRESH to REG disables the converter. See Figure 1 and the Typical Operating Circuit.
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12V PWM Controller with Hot-Swap MAX5950
Power-Good Sequencing (PGOOD, SENSE)
The PGOOD outputs and DCENI inputs can be daisychained to generate power sequencing. The PGOOD output is pulled high when the voltage at SENSE is above VREF (800mV typ). Connect a resistive divider from the power-supply output voltage to SENSE to AGND to set the power-good threshold. See Figure 1 and the Typical Operating Circuits. If the current-limit threshold is exceeded for eight cumulative clock cycles (NCL), the device shuts down (both DH and DL are pulled low) for 512 clock cycles (hiccup timeout) and restarts with a soft-start sequence. If three consecutive cycles pass without a current-limit event, the count of NCL is cleared (Figure 2). Hiccup mode protects against continuous output short circuit.
Thermal-Overload Protection
The MAX5950 features an integrated thermal-overload protection with temperature hysteresis. Thermal-overload protection limits the total power dissipation in the device and protects it in the event of an extended thermal fault condition. When the die temperature exceeds +135C, an internal thermal sensor shuts down the device, turning off the power MOSFETs and allowing the die to cool. After the die temperature falls by +15C, the part restarts with a soft-start sequence.
Error Amplifier
The output of the internal error amplifier (COMP) is available for frequency compensation (see the Compensation Design Guidelines section). The inverting input is FB; the output is COMP. The error amplifier has an 80dB open-loop gain and a 2.5MHz GBW product. See the Typical Operating Characteristics section for the Open-Loop Gain and Phase vs. Frequency graph.
PWM Comparator
An internal ramp is compared against the output of the error amplifier to generate the PWM signal. The amplitude of the ramp, VRAMP, is 1.8V.
Hot-Swap Controller Design Procedures
Setting the Undervoltage Lockout
Connect an external resistive divider from IN to HUVLO to AGND to override the internal hot-swap UVLO divider. The rising threshold at HUVLO is set to 1.220V with 120mV hysteresis. First, select the HUVLO to AGND resistor (R2), then calculate the resistor from IN to HUVLO (R1) using the following equation: VIN R1 = R2 x - 1 VHUVLO where VIN is the input voltage at which the hot-swap controller needs to turn on, VHUVLO = 1.220V, and R2 is chosen to be less than 20k (see Figure 3). Leave HUVLO unconnected for the default hot-swap UVLO threshold. In this case, an internal voltagedivider monitors the supply voltage at IN and allows startup when IN rises above 7V (typ).
IN
Output Short-Circuit Protection (Hiccup Mode)
The current-limit circuit employs a lossless valley current-limiting algorithm that uses the MOSFET's on-resistance as the current-sensing element. Once the high-side MOSFET turns off, the voltage across the lowside MOSFET is monitored. If the voltage across the low-side MOSFET (RDS(ON) x I INDUCTOR ) does not exceed the current-limit threshold, the high-side MOSFET turns on normally at the start of the next cycle. If the voltage across the low-side MOSFET exceeds the current-limit threshold just before the beginning of a new PWM cycle, the controller skips that cycle. During severe overload or short-circuit conditions, the switching frequency of the device appears to decrease because the on-time of the low-side MOSFET extends beyond a clock cycle.
CURRENT LIMIT
IN COUNT OF 8 NCL CLR
INITIATE HICCUP TIMEOUT NHT
R1 HUVLO R2
IN COUNT OF 3 NCLR CLR
Figure 2. Hiccup-Mode Block Diagram 16
Figure 3. External Hot-Swap UVLO Divider
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12V PWM Controller with Hot-Swap
n-Channel MOSFET Selection
Select the external n-channel MOSFET according to the application's current level. The MOSFET's on-resistance (RDS(ON)) should be chosen low enough to have a minimum voltage drop at full load to limit the MOSFET power dissipation. High RDS(ON) can cause output ripple if the board has pulsing loads. Determine the device power-rating requirement to accommodate a short circuit on the board at startup. In normal operation, the product of pass MOSFET RDS(ON) and IIN should not exceed the circuit-breaker threshold (600mV).
Setting the Output Voltage
Connect a resistive divider from OUT to FB to AGND to set the output voltage. First, calculate the resistor from OUT to FB using the guidelines in the Compensation Design Guidelines section. Once R3 is known, calculate R4 using the following equation: R4 = R3 VOUT - 1 VFB
MAX5950
where VFB = 0.8V.
PWM Controller Design Procedures
Setting the Undervoltage Lockout
Connect an external resistive divider from PWM_IN to PUVLO to AGND to override the internal PWM UVLO divider. The rising threshold at PUVLO is set to 1.220V with 120mV hysteresis. First, select the PUVLO to AGND resistor (R2), then calculate the resistor from PWM_IN to PUVLO (R1), using the following equation: VPWM _ IN R1 = R2 x - 1 VPUVLO where VPWM_IN is the input voltage at which the converter needs to turn on, VPUVLO = 1.220V, and R2 is chosen to be less than 20k (see Figure 4). Leave PUVLO unconnected for the default PWM UVLO threshold. In this case, an internal voltage-divider monitors the supply voltage at PWM_IN and allows startup when PWM_IN rises above 7V (typ).
Inductor Selection
Three key inductor parameters must be specified for operation with the MAX5950: inductance value (L), peak inductor current (IPEAK), and inductor saturation current (ISAT). The minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current (IP-P). Higher IP-P allows for a lower inductor value. A lower inductance value minimizes size and cost and improves large-signal and transient response, but reduces efficiency due to higher peak currents and higher peak-topeak output voltage ripple for the same output capacitor. A higher inductance increases efficiency by reducing the ripple current; however, resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels, especially when the inductance is increased without also allowing for larger inductor dimensions. A good rule of thumb is to choose IP-P equal to 30% of the full-load current. Calculate the inductor using the following equation: L= VOUT (VIN - VOUT ) VIN x fSW x IP-P
PWM_IN
R1 PUVLO R2
Figure 4. External PWM UVLO Divider
VIN and VOUT are typical values so that efficiency is optimum for typical conditions. The switching frequency is programmable between 100kHz and 1000kHz (see the Oscillator/Synchronization Input (SYNCIN)/ Synchronization Output (SYNCOUT) section). The peak-to-peak inductor current, which reflects the peakto-peak output ripple, is worst at the maximum input voltage. See the Output Capacitor Selection section to verify that the worst-case output current ripple is acceptable. The inductor saturation current (I SAT) is also important to avoid runaway current during continuous output short-circuit conditions. Select an inductor with an ISAT specification higher than the maximum peak current.
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12V PWM Controller with Hot-Swap MAX5950
Input-Capacitor Selection
The discontinuous input current of the buck converter causes large input ripple currents, therefore the input capacitor must be carefully chosen to withstand the input ripple current and maintain the input voltage ripple within design requirements. The total voltage ripple is the sum of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the input capacitor), which peaks at the end of the ON cycle. Calculate the input capacitance and ESR required for a specified ripple using the following equations: ESR = VESR IP-P ILOAD(MAX) + 2 The allowable deviation of the output voltage during load transients also affects the choice of output capacitance, its ESR, and its equivalent series inductance (ESL). The output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. The response time (tRESPONSE ) depends on the closed-loop bandwidth of the converter (see the Compensation Design Guidelines section). The resistive drop across the output capacitor's ESR, the drop across the capacitor's ESL, and the capacitor discharge cause a voltage droop during the load step. Use a combination of low-ESR tantalum/aluminum electrolyte and ceramic capacitors for better load transient and voltage-ripple performance. Surface-mount capacitors and capacitors in parallel help reduce the ESL. Keep the maximum output-voltage deviation below the tolerable limits of the electronics being powered. Use the following equations to calculate the required ESR, ESL, and capacitance value during a load step: ESR = VESR ISTEP xt I COUT = STEP RESPONSE VQ VESL x t STEP ISTEP
VOUT ILOAD(MAX) x VPWM _ IN CIN = VQ x fSW where IP-P = (VPWM _ IN - VOUT ) x VOUT VPWM _ IN x fSW x L
ILOAD(MAX) is the maximum output current, IP-P is the peakto-peak inductor current, and fSW is the switching frequency. The MAX5950 includes UVLO hysteresis to avoid possible unintentional chattering during turn-on. Use additional bulk capacitance if the input source impedance is high. When the input voltage is near the UVLO, additional input capacitance helps avoid possible undershoot below the UVLO threshold during transient loading.
ESL =
where ISTEP is the load step, tSTEP is the rise time of the load step, and tRESPONSE is the response time of the controller.
Output-Capacitor Selection
The allowed output voltage ripple and the maximum deviation of the output voltage during load steps determine the required output capacitance and its ESR. The output ripple is mainly composed of VQ (caused by the capacitor discharge) and VESR (caused by the voltage drop across the equivalent series resistance (ESR) of the output capacitor). The equations for calculating the peak-to-peak output voltage ripple are: IP-P 8 x COUT x fSW I VESR = ESR x P-P 2 VQ = VESR and VQ are not directly additive since they are out of phase from each other. If using ceramic capacitors, which generally have low ESR, VQ dominates. If using electrolytic capacitors, VESR dominates.
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Setting the Current Limit
Connect a 25k to 175k resistor, RILIM, from ILIM to AGND to program the valley current-limit threshold from 50mV to 350mV. ILIM sources 20A out to RILIM. The resulting voltage divided by 10 is the valley current-limit threshold. The MAX5950 uses a valley current-sense method for current limiting. The voltage drop across the low-side MOSFET due to its on-resistance is used to sense the inductor current. The voltage drop across the low-side MOSFET at the valley point and at ILOAD(MAX) is: I VVALLEY = RDS(ON) (T) x ILOAD(MAX) - P -P 2 RDS(ON) is the on-resistance of the low-side MOSFET, which is temperature dependent, I LOAD(MAX) is the maximum DC load current, and IP-P is the peak-topeak inductor current.
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12V PWM Controller with Hot-Swap
Compensation Design Guidelines
1.5 1.4 1.3 VILIM AND RDS(ON) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -40 -15 10 35 60 85 TEMPERATURE (C)
MAX5950
Figure 5. Current-Limit Trip Point and RDS(ON) vs. Temperature
The 20A current source, ILIM reference current, has a temperature coefficient of 3333ppm/C. This allows the valley current-limit threshold: RILIM x 20A (T) 10 to track and compensate for the increase in the synchronous MOSFET's RDS(ON) with increasing temperature range. MOSFETs typically have a temperature coefficient of 3000ppm/C to 7000ppm/C. Refer to the MOSFET data sheet for a device-specific temperature coefficient. At a given temperature, the calculated VVALLEY must be less than the minimum valley current-limit threshold specified. Figure 5 illustrates the effect of the MAX5950 ILIM reference current temperature coefficient to compensate for the variation of the MOSFET RDS(ON) over the operating junction temperature range.
The MAX5950 uses a voltage-mode control scheme that regulates the output voltage by comparing the error amplifier output (COMP) with an internal ramp to produce the required duty cycle. The output lowpass LC filter creates a double pole at the resonant frequency, which has a gain drop of -40dB/decade. The compensation network must compensate for this gain drop and phase shift to achieve a stable closed-loop system. The basic regulator loop consists of a power modulator, an output feedback divider, and a voltage-error amplifier. The power modulator has a DC gain set by VIN/VRAMP, with a double pole and a single zero set by the output inductance (L), the output capacitance (COUT), and its ESR. Below are equations that define the power modulator: VIN GMOD(DC) = VRAMP 1 fLC = 2 L x COUT fZESR = 1 2 x COUT x RESR
Power-MOSFET Selection
When selecting MOSFETs, consider the total gate charge, R DS(ON) , power dissipation, the maximum drain-to-source voltage, package thermal impedance, and desired current limit. The product of the MOSFET gate charge and on-resistance is a figure of merit, with a lower number signifying better performance. Choose MOSFETs optimized for high-frequency switching applications. The average gate-drive current from the MAX5950's output is proportional to the frequency and gate charge required to drive the MOSFET. The power dissipated in the MAX5950 is proportional to the input voltage and the average drive current (see the Power Dissipation section).
The switching frequency is programmable between 100kHz and 1000kHz by an external resistor at RT. The crossover frequency (fC), which is the frequency when the closed-loop gain is equal to unity, should be set to fSW / 10 or fGBW / 25, whichever is lower. The error amplifier must provide a gain-and-phase boost to compensate for the rapid gain-and-phase loss from the LC double pole. This is accomplished by utilizing type 3 compensation (see Figures 6 and 7) that introduces two zeros and three poles into the control loop. The error amplifier has a low-frequency pole (fP1) at the origin; two zeros at: 1 fZ1 = 2 x R5 x C7 and fZ2 = 1 2 x R3 x C6
and higher frequency poles at: 1 fP2 = 2 x R6 x C6 and fP3 = 1 2 x R5 x C8
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19
12V PWM Controller with Hot-Swap MAX5950
C8 C8
R5 C6 R6 R3 VOUT R4 REF EA
C7 C6 R6 R3 VOUT COMP R4 REF
R5
C7
EA
COMP
GAIN (dB)
CLOSED-LOOP GAIN EA GAIN
GAIN (dB)
CLOSED-LOOP GAIN
EA GAIN
fZ1 fZ2
fC
fP2 fP3
FREQUENCY
fZ1 fZ2
fP2
fC
fP3
FREQUENCY
Figure 6. Error Amplifier Compensation Circuit (Closed-Loop and Error-Amplifier Gain Plot) for Ceramic Capacitors
Figure 7. Error-Amplifier Compensation Circuit (Closed-Loop and Error-Amplifier Gain Plot) for Higher ESR Output Capacitors
Compensation when fC < fZESR Figure 6 shows the error-amplifier feedback, as well as its gain response for circuits that use low-ESR output capacitors (ceramic). In this case, fC occurs before fZESR. fZ1 is set to 0.5 x fLC and fZ2 is set to fLC to compensate for the gain-and-phase loss due to the double pole. Choose the inductor (L) and output capacitor (C OUT ) as described in the Inductor Selection and Output-Capacitor Selection sections. Pick a value for feedback resistor R5 in Figure 6 (values between 1k and 10k are adequate). C7 is then calculated as: C7 = 1 2 x 0.5 x fLC x R5
Since GEA(fC) x GMOD(fC) = 1, C6 is calculated by: f x L x COUT x 2 C6 = C R5 x GMOD(DC) R3 is then calculated as: R3 1 2 x fLC x C6
fP2 is set at 1/2 the switching frequency (f SW). R6 is then calculated by: R6 = 1 2 x C6 x 0.5fSW
fC occurs between fZ2 and fP2. The circuit is implemented with C7 > C8 and R3 > R6, in which case the error-amplifier gain (GEA) at fC is due primarily to C6 and R5. Therefore: GEA(fc) = 2 x fC x C6 x R5 The modulator gain at fC is: GMOD(fC) = GMOD(DC) (2) x L x COUT x fC2
2
fP3 is set at 5xfC. Therefore, C8 is calculated as: C8 = 1 2 x R5 x 5 x fC
Compensation when fC > fZESR For larger ESR capacitors such as tantalum and aluminum electrolytic, fZESR can occur before fC. If fC > f ZESR , f C occurs between f P2 and f P3 . f Z1 and f Z2 remain the same as before; however, fP2 is now set equal to fZESR. The output capacitor's ESR zero fre-
20
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12V PWM Controller with Hot-Swap
quency is higher than fLC, but lower than the closedloop crossover frequency. The equations that define the error amplifier's poles and zeroes (fZ1, fZ2, fP1, fP2, and fP3) are the same as before. However, fP2 is now lower than the closed-loop crossover frequency. Figure 7 shows the error-amplifier feedback, as well as its gain response for circuits that use higher ESR output capacitors (tantalum, aluminum electrolytic, etc.) Pick a value for feedback resistor R5 in Figure 7 (values between 1k and 10k are adequate). C7 is then calculated as: 1 C7 = 2 x 0.5 x fLC x R5 The circuit is implemented with C7 >> C8 and R3 >> R6, in which case the error-amplifier gain between fP2 and fP3 is approximately equal to: R5 R6 The modulator gain at fC is: GMOD(fC) = GMOD(DC) (2) x L x COUT x fC2
2
Hot-Swap Controller Applications Information
Additional External Gate Capacitance
External capacitance can be added from the gate of the external MOSFET to AGND to reduce the dv/dt of the PWM controller input voltage (VPWM_IN), decreasing the hot-swap inrush current. Add a 10k resistor in series with the added gate capacitor to prevent degrading the device turn-off response to a fault condition.
MAX5950
Layout Considerations
To take advantage of the switch response time to an output fault condition, it is important to keep all traces as short as possible and to maximize the high-current trace width to reduce the effect of undesirable parasitic inductance. Use a ground plane to minimize impedance and inductance. Minimize the trace length that connects to IN and HSENSE (< 10mm), and ensures accurate current sensing with Kelvin connections. When the output is short circuited, the voltage drop across the external MOSFET becomes large. Hence, the power dissipation in the switch increases, as does the die temperature. An efficient way to achieve good power dissipation on a surface-mount package is to lay out two copper pads directly under the MOSFET package on both sides of the board. Connect the two pads to the ground plane through vias, and use enlarged copper mounting pads on the top side of the board.
Since GEA(fC) x GMOD(fC) = 1, R6 can then be calculated as: R6 R5 x GMOD(DC) (2)2 x L x COUT x fC2
PWM Controller Applications Information
Power Dissipation
The 32-pin TQFN thermally enhanced package can dissipate 2.7W. Calculate power dissipation in the MAX5950 as a product of the input voltage and the total REG output current (IREG). IREG includes quiescent current (IQ) and gate-drive current (IDREG): PD = VIN x IREG IREG = IQ + [fSW x (QG1 + QG2)] where QG1 and QG2 represent the total gate charge of the low-side and high-side external MOSFETs, fSW is the switching frequency of the converter, and IQ is the quiescent current of the device at the switching frequency. Use the following equation to calculate the maximum power dissipation (PDMAX) in the chip at a given ambient temperature (TA): PDMAX = 34.5 x (150 - TA)..........mW
fP2 is set to fZESR. C6 is then calculated as: C6 = COUT x ESR R6
R3 is then calculated as: R3 1 2 x fLC x C6
fP3 is set at 5xfC. Therefore, C8 is calculated as: C8 = 1 2 x R5 x 5 x fC
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21
12V PWM Controller with Hot-Swap MAX5950
PC Board Layout Guidelines
Use the following guidelines to layout the switching voltage regulator: 1) Place the PWM_IN and DREG bypass capacitors close to the MAX5950 PGND pin. Place the REG bypass capacitor close to the AGND pin. 2) Minimize the area and length of the high-current loops from the input capacitor, upper switching MOSFET, inductor, and output capacitor back to the input capacitor negative terminal. 3) Keep short the current loop formed by the lower switching MOSFET, inductor, and output capacitor. 4) Keep AGND and PGND isolated and connect them at one single point close to the negative terminal of the input filter capacitor. 5) Run current-sense lines CS+ and CS- close to each other to minimize the loop area. 6) Avoid long traces between the REG/DREG bypass capacitors, driver output of the MAX5950, MOSFET gates, and PGND. Minimize the loop formed by the REG bypass capacitors, bootstrap diode, bootstrap capacitor, the MAX5950, and upper MOSFET gate. 7) Place the bank of output capacitors close to the load. 8) Distribute the power components evenly across the board for proper heat dissipation. 9) Provide enough copper area at and around the switching MOSFETs and the inductor to aid in thermal dissipation. 10) Use 2oz copper to keep the trace inductance and resistance to a minimum. Thin copper PC boards can compromise efficiency since high currents are involved in the application. Also, thicker copper conducts heat more effectively, thereby reducing thermal impedance.
Simplified Block Diagrams
HOT-SWAP CONTROLLER
IN
MAX5950
HUVLO 10ms RISINGEDGE DELAY FILTER AGND 1.220V EN CHARGE PUMP IOUT GATE
PWREN REG THERMAL SHUTDOWN 10A 165ms RISING EDGE DELAY FILTER IN 0.6V HSENSE 5V PWM_IN
DCENO
PWRFLT S MPWRGD 165ms RISINGEDGE DELAY FILTER R Q SET DOMINANT
PGI
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12V PWM Controller with Hot-Swap
Simplified Block Diagrams (continued)
PWM CONTROLLER
PWM_IN PUVLO THRESH DCENI
MAX5950
MAX5950
LDO REG EN 1.220V VREGOK STARTUP 0.8V REF RES CSSHDN CLK DIGITAL SOFT-START OVL E/A FB DH R COMP SYNCIN RT EN RAMP OSC 0.3V CLK PGND STARTUP REF CPWM IMAX Q SET DOMINANT S REG 10A LX DREG DL RES OVERLOAD MANAGEMENT IMAX CLK CURRENTLIMIT SET ILIM THERMAL SHUTDOWN REG 10A AGND
CS+
REF
BST
SYNCOUT
SENSE
PGOOD
______________________________________________________________________________________
23
12V PWM Controller with Hot-Swap MAX5950
Typical Operating Circuits
PCIe EXPRESSMODULE (TRACKING)
(SHORT PIN)
+3.3VAUX
+12V CIN PRSNT (SHORT PIN)
CBST IN HUVLO L PWREN PWRFLT MPWRGD GND PWREN PWRFLT LX CSVOUT1 GATE HSENSE PWM_IN REG DREG BST DH Q2
MAX5950
MPWRGD
DL CS+
Q1
COUT
C6
R3
R6
THRESH PUVLO PGI DCENO DCENI AGND PGOOD SYNCIN SYNCOUT RRT RT ILIM STARTUP RILIM COMP
PGND FB SENSE C8 C7 R5 R4
PCIe EXPRESSMODULE SLOT
CBST IN REG DREG BST DH Q2 L LX CSVOUT2
MAX5951
DL CS+
Q1
COUT
C6
R3
R6
THRESH PUVLO DCENI AGND PGOOD SYNCIN SYNCOUT RT ILIM STARTUP COMP
PGND FB SENSE C8 C7 R5 R4
RRT
RILIM
24
______________________________________________________________________________________
12V PWM Controller with Hot-Swap
Typical Operating Circuits (continued)
PCIe EXPRESSMODULE (STARTUP SEQUENCING)
+3.3VAUX (SHORT PIN)
MAX5950
+12V CIN (SHORT PIN) PRSNT
CBST IN HUVLO L PWREN PWRFLT MPWRGD GND PWREN PWRFLT MPWRGD CS+ THRESH PUVLO PGI DCENO DCENI PCIe EXPRESSMODULE SLOT RRT RILIM R5 AGND PGOOD SYNCIN SYNCOUT RT ILIM STARTUP COMP PGND FB SENSE C8 C7 R4 R6 LX CSVOUT1 GATE HSENSE PWM_IN REG DREG BST DH Q2
MAX5950
DL
Q1
COUT
C6
R3
CBST IN REG DREG BST DH Q2 L LX CSVOUT2
MAX5951
DL CS+
Q1
COUT
C6
R3
R6
THRESH PUVLO DCENI AGND PGOOD SYNCIN SYNCOUT RT ILIM STARTUP COMP
PGND FB SENSE C8 C7 R5 R4
RRT
RILIM
______________________________________________________________________________________
25
12V PWM Controller with Hot-Swap MAX5950
Typical Operating Circuits (continued)
PCIe EXPRESSMODULE (PGOOD SEQUENCING)
+3.3VAUX (SHORT PIN)
+12V CIN (SHORT PIN) PRSNT
CBST IN HUVLO L PWREN PWRFLT MPWRGD GND PWREN PWRFLT MPWRGD CS+ THRESH PUVLO PGI PCIe EXPRESSMODULE SLOT RRT RILIM R5 DCENO DCENI AGND PGOOD SYNCIN SYNCOUT RT ILIM STARTUP COMP PGND FB SENSE C8 C7 R4 R6 LX CSVOUT1 GATE HSENSE PWM_IN REG DREG BST DH Q2
MAX5950
DL
Q1
COUT
C6
R3
CBST IN REG DREG BST DH Q2 L LX CSVOUT2
MAX5951
DL CS+ THRESH PUVLO DCENI AGND PGOOD SYNCIN SYNCOUT RT ILIM STARTUP COMP PGND FB SENSE C8
Q1
COUT
C6
R3
R6
RRT
RILIM R5
C7
R4
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12V PWM Controller with Hot-Swap
Typical Operating Circuits (continued)
MAX5950
USING EXTERNAL CURRENT-SENSE RESISTOR
+3.3VAUX (SHORT PIN)
+12V CIN (SHORT PIN) PRSNT
CBST IN HUVLO PWREN PWRFLT MPWRGD GND PWREN PWRFLT GATE HSENSE PWM_IN REG DREG BST DH Q2 L LX DL Q1 COUT C6 R3 VOUT1
MAX5950
MPWRGD THRESH PUVLO PGI PCIe EXPRESSMODULE SLOT DCENO DCENI AGND PGOOD SYNCIN SYNCOUT RT ILIM STARTUP COMP
CS-
CS+ PGND FB SENSE C8
R6
R4 R5 C7
RRT
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________
27
12V PWM Controller with Hot-Swap MAX5950
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
M. Quijano

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